The synthesizable micro PLL is a small synthesizable general-purpose PLL that multiplies the reference clock by any integer or fractional-N value from 1 to 500K. It supports reference clock frequencies as low as 32KHz and output frequencies as high as 3GHz. It can stay locked to the reference clock while it changes over a 10:1 frequency range. Because it is synthesizable, it can support spreading as well as other modulation profiles. It is relatively low power, very fast locking and can quickly restart from a sleep mode.

The synthesizable micro DLL is a small synthesizable DLL with a master and multiple slaves topology.  It can support reference frequencies typically in the range of 500MHz to 3GHz and track reference changes over an 8:1 frequency range while providing 9-bit accuracy in slave delay programming. Slave delays can be changed glitch free and the DLL can quickly restart from a sleep mode. It has a very small zero code offset that can be precisely cancelled.

  About True Circuits DDR PHYs
The DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read gate and data eye timing are also continuously adjusted. Fully automatic training is managed by a light weight special purpose processor and includes multi-cycle write leveling and read gate training and also read/write data eye training, including PHY Vref and DRAM Vref settings.

The PHY employs a localized and optimized PHY-to-memory controller interface to ease timing closure. The circuitry in each pin is able to measure the data eye and jitter, and calculate flight delays. The PHY also includes a full speed read/write BIST, which tests the complete read and write paths of every pin simultaneously with pseudo-random data.

Remarkable physical flexibility allows the PHY to adapt to each customer's die floorplan and package constraints, yet is verified and delivered as a unit for easy timing closure with no assembly required. The PHY supports LPDDR5, DDR4, LPDDR4, DDR3 and LPDDR3, and is DFI 5.1 compliant.  When combined with an appropriate DDR memory controller, a complete and fully-automatic DDR system is realized.

The True Circuits DDR PHY is silicon proven and immediately available for customer delivery in TSMC's 28/22nm HPC/HPC+ processes. The PHY is also available upon request in a variety of TSMC processes from 40nm to 4nm. Interested customers can obtain more product information on the web at www.truecircuits.com/ddr_phy.html or by contacting True Circuits at Email Contact.

About True Circuits
True Circuits develops and markets a broad range of industry leading PLLs, DLLs and DDR PHY hard macros for ICs for the semiconductor, systems and electronics industries. TCI's robust state-of-the-art circuits, methodical and proven design strategy, and close association with the world's leading foundries, IDMs, and design services companies allow the company to quickly and reliably create new and innovative designs in a variety of advanced process technologies. Over the last 25 years, True Circuits has distinguished itself as the technology leader in the timing IP space, and its PLLs and DLLs are used extensively around the world in its customers' products with production volumes well into the billions.

True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los Altos, California 94022 and can be found on the web at www.truecircuits.com. Product inquiries can be made by calling the company directly at (650) 949-3400 or via e-mail at Email Contact.

Press Contact: Kimberly Toan, True Circuits, Inc., (650) 949-3400, Ext. 3404, Email Contact.

Acronyms and definitions:

ASIC         Application Specific IC                                                 

IoT            Internet of Things                     

DLL           Delay-Locked Loop                                                      

IP              Intellectual Property

DDR         Double Data Rate                                                         

ONFI        Open NAND Flash Interface

FPGA       Field Programmable Gate Array                               

PLL           Phase-Locked Loop

IC              Integrated Circuit                                                          

SoC          System on a Chip

JSPICE is a trademark of True Circuits, Inc.

The Precision PLL is a trademark of True Circuits, Inc.

The micro PLL is a trademark of True Circuits, Inc.

The micro DLL is a trademark of True Circuits, Inc.

The IoT PLL is a trademark of True Circuits, Inc.

The Ultra PLL is a trademark of True Circuits, Inc.

The True Circuits logo is a trademark of True Circuits, Inc.

All other trademarks and tradenames are the property of their respective owners.