“The SEGGER J-Link is the most widely used line of debug probes in the market,” says Ivo Geilenbruegge, Managing Director of SEGGER. “J-Links have provided solid value to embedded development for over 15 years. Unparalleled performance, an extensive feature set, a multitude of supported CPUs, and compatibility with popular development environments — all this makes J-Link an unbeatable choice. We’re happy to add Cadence Tensilica IP to the list of supported cores.”

“The drive to push intelligence further out to the edge means that more and more MCUs and SoCs contain our Tensilica CPU and DSP IP,” said George Wall, Group Director of Product Marketing for Tensilica Xtensa Processor IP at Cadence. “The new SEGGER implementation enables us to use the J-Link GDB Server as a native J-Link driver in our Tensilica Xplorer Integrated Development Environment (IDE), resulting in a significant performance increase. As a result, customers will be able to debug their firmware running on Tensilica cores more quickly.”

The Cadence Tensilica core support has already been added to the J-Link software pack, which is available for download from the SEGGER website.

For more information on J-Link, please visit:
https://www.segger.com/products/debug-probes/j-link/

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About SEGGER
SEGGER Microcontroller GmbH has three decades of experience in Embedded Systems, producing cutting-edge RTOS and Software Libraries, J-Link and J-Trace debug and trace probes, a line of Flasher In-System Programmers and software development tools.

SEGGER's all-in-one solution emPower OS provides an RTOS plus a complete spectrum of software libraries including communication, security, data compression and storage, user interface software and more. Using emPower OS gives developers a head start, benefiting from decades of experience in the industry.