RISC-V Foundation Announces Agenda for the “Getting Started with RISC-V” Roadshow in China
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RISC-V Foundation Announces Agenda for the “Getting Started with RISC-V” Roadshow in China

The roadshow will feature live demonstrations and presentations from RISC-V Foundation members, includes free admission

BEIJING — (BUSINESS WIRE) — April 22, 2019 — RISC-V Foundation:

WHAT: The RISC-V Foundation, a non-profit corporation controlled by 235 member companies to drive a new era of processor innovation via the adoption and implementation of the free and open RISC-V ISA, announces the agenda for its “Getting Started with RISC-V” events across China. As part of this program, RISC-V members will host presentations and live demonstrations showcasing the ecosystem’s overall explosive growth and discuss the Foundation’s increasing footprint particularly within China and the greater APAC region. This event also offers an opportunity for attendees to speak with RISC-V experts and other local RISC-V enthusiasts about the increased commercial adoption and growing number of implementations.

WHERE: The Crowne Plaza Landmark in Shenzhen; the Sheraton Chengdu Lido Hotel in Chengdu; the Hyatt on the Bund; Alibaba in Hangzhou; the Bellagio in Shanghai; the Crowne Plaza Zhongguancun in Beijing.

WHEN: Monday, May 6; Wednesday, May 8; Monday, May 13; Tuesday, May 14; and Thursday, May 16

DETAILS: The RISC-V Foundation in collaboration with the Linux Foundation is hosting a series of free, one-day “Getting Started with RISC-V” events. These non-consecutive one-day seminars will feature 13 RISC-V Foundation members including Alibaba Group, Andes Technology, Codasip, GreenWaves Technologies, Nervos, Nuclei System, NXP, PerfXLab, SiFive, Syntacore, Tangram, UC TECH IP and UltraSoC.

Getting Started with RISC-V Agenda

Welcome and Check in

Introduction to RISC-V

Nuclei RISC-V Solution Paves the Way to Your Application Defined Chip

Pushing Data from the Edge to the Cloud with RISC-V Ecosystem

Productivity Tools for Automated Generation of RISC-V Processors

Break

How to Choose Your AIoT RISC-V Core? 如何選擇�nbsp;的AIoT RISC-V�bsp;�心?

Perf-V: The Cost-Effective Development Board for RISC-V Community

Enabling AIoT with RISC-V on a Battery for Years

Lunch

SCRx Family of the RISC-V Compatible Processor IP

RISC-V Enters the Mainstream – Next Steps for the Ecosystem

TG403: a High-Performance Secure RISC-V Based MCU for Embedded Applications

Break

Expanding RISC-V Ecosystem for China Adoption 扩展RISC-V生态系统，助力中国市场

Innovation Unleashed: Solutions and Silicon Enabling the Intelligent Edge and Linux

CKB-VM: a Blockchain Focused, General-Purpose Applicable Software Sandbox System Based on RISC-V

Innovation Thrust

*Please note, the Nervos and UC TECH IP presentations will only take place at the Hangzhou event.

Each event is admission free, see below to register.

To learn more about the RISC-V China Roadshow, please visit: https://www.lfasiallc.com/events/risc-v-china-roadshow-2019/

For press interested in attending and scheduling meetings with the RISC-V Foundation and member companies, please email: risc-v@racepointglobal.com.

To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit: https://riscv.org.

About RISC-V Foundation

RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 235 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.


Contact:

Allison DeLeo
Racepoint Global for RISC-V Foundation
Phone: +1 (415) 694-6700
Email: Email Contact