The roadshow will feature live demonstrations and presentations from RISC-V Foundation members, includes free admission
BEIJING — (BUSINESS WIRE) — April 22, 2019 — RISC-V Foundation:
WHAT: The RISC-V Foundation, a non-profit corporation controlled by 235 member companies to drive a new era of processor innovation via the adoption and implementation of the free and open RISC-V ISA, announces the agenda for its “Getting Started with RISC-V” events across China. As part of this program, RISC-V members will host presentations and live demonstrations showcasing the ecosystem’s overall explosive growth and discuss the Foundation’s increasing footprint particularly within China and the greater APAC region. This event also offers an opportunity for attendees to speak with RISC-V experts and other local RISC-V enthusiasts about the increased commercial adoption and growing number of implementations.
WHERE: The Crowne Plaza Landmark in Shenzhen; the Sheraton Chengdu Lido Hotel in Chengdu; the Hyatt on the Bund; Alibaba in Hangzhou; the Bellagio in Shanghai; the Crowne Plaza Zhongguancun in Beijing.
WHEN: Monday, May 6; Wednesday, May 8; Monday, May 13; Tuesday, May 14; and Thursday, May 16
DETAILS: The RISC-V Foundation in collaboration with the Linux Foundation is hosting a series of free, one-day “Getting Started with RISC-V” events. These non-consecutive one-day seminars will feature 13 RISC-V Foundation members including Alibaba Group, Andes Technology, Codasip, GreenWaves Technologies, Nervos, Nuclei System, NXP, PerfXLab, SiFive, Syntacore, Tangram, UC TECH IP and UltraSoC.
Getting Started with RISC-V Agenda
Welcome and Check in
- When: 8:30 a.m. – 9 a.m. GMT+8
Introduction to RISC-V
- When: 9 a.m. – 9:20 a.m. GMT+8
- Who: RISC-V Foundation
Nuclei RISC-V Solution Paves the Way to Your Application Defined Chip
- When: 9:20 a.m. – 9:40 a.m. GMT+8
- Who: Nuclei System
Pushing Data from the Edge to the Cloud with RISC-V Ecosystem
- When: 9:40 a.m. – 10 a.m. GMT+8
- Who: Alibaba Group
Productivity Tools for Automated Generation of RISC-V Processors
- When: 10 a.m. – 10:20 a.m. GMT+8
- Who: Codasip
Break
- When: 10:20 a.m. – 10:50 a.m. GMT+8
How to Choose Your AIoT RISC-V Core? 如何選擇�nbsp;的AIoT RISC-V�bsp;�心?
- When: 10:50 a.m. – 11:10 a.m. GMT+8
- Who: Andes Technology
Perf-V: The Cost-Effective Development Board for RISC-V Community
- When: 11:10 a.m. – 11:30 a.m. GMT+8
- Who: PerfXLab
Enabling AIoT with RISC-V on a Battery for Years
- When: 11:30 a.m. – 11:50 a.m. GMT+8
- Who: GreenWaves Technologies
Lunch
- When: 11:50 a.m. – 1 p.m. GMT+8
SCRx Family of the RISC-V Compatible Processor IP
- When: 1 p.m. – 1:20 p.m. GMT+8
- Who: Syntacore
