-
The Updated Status of RISC-V SW
- When: 09:30 – 09:55
- Who: Kito Cheng and Greentime Hu, Andes Technology
-
RISC-V Perf Tool Status
- When: 10:00 – 10:15
- Who: Alan Kao, Andes Technology
-
Linux on RISC-V – Fedora and Firmware Status Update
- When: 10:15 – 10:40
- Who: Wei Fu, Red Hat
-
Toolchain: Compiler Support for Linker Relaxation in RISC-V
- When: 11:10 – 11:35
- Who: Shiva Chen and Hsiangkai Wang, Andes Technology
-
Toolchain: Enhanced LLVM Support For RISC-V
- When: 11:40 – 12:05
- Who: Chris Jones and Zdenek Prikryl, Codasip
-
Toolchain: RISC-V Configurability in Compliance Test Framework
- When: 12:10 – 12:35
- Who: Radek Hajek and Milan Skala, Codasip
-
Datacenter Processors with OmniXtend Interfaces for Shared Memory
and AI Workload Acceleration
- When: 14:05 – 14:30
- Who: Zvonimir Bandic, Western Digital
-
PolarFire SoC FPGA – AMP Capable Solution for Both Deterministic
Real-Time and Rich OS Support
- When: 14:50 – 15:05
- Who: Vishakh Rayapeta, Microsemi
-
Enabling Embedded Intelligence
- When: 15:05 – 15:30
- Who: Jack Kang, SiFive
-
SCRx Family of the RISC-V Compatible Core IP by Syntacore
- When: 15:35 – 16:00
- Who: Alexander Redkin and Pavel Khabarov, Syntacore
To register for the event, please visit: https://tmt.knect365.com/risc-v-workshop-taiwan/purchase/select-package. To learn more about sponsorship opportunities, please visit: https://tmt.knect365.com/risc-v-workshop-taiwan/sponsor.
For press interested in attending, please email:
risc-v@racepointglobal.com
to receive your complimentary pass. To learn more about the RISC-V
Foundation, its open, free architecture and membership information,
please visit:
https://riscv.org .
