-
User Mode Interrupts: a Must for Securing Embedded Systems
- When: 16:00 – 16:30 CET
- Who: Prof. Sandro Pinto, Universidade do Minho; Cesare Garlati, prpl Foundation and Hex Five Security
-
Embracing a System Level Approach: Combining Arm & RISC-V in
Heterogeneous Designs
- When: 16:30 – 17:00 CET
- Who: Gajinder Panesar, UltraSoC
-
RISC-V: High Performance Embedded SweRV Core Microarchitecture,
Performance and Implementation Challenges
- When: 17:00 – 17:30 CET
- Who: Dr. Zvonimir Bandic, Western Digital
Class 5.2: RISC-V Workshop (Feb. 27)
-
How to Build a RISC-V Embedded System In Just 30 Minutes
- When: 9:30 – 10:30 CET
- Who: Cesare Garlati, prpl Foundation and Hex Five Security; Drew Barbier, SiFive
-
How to Secure a RISC-V Embedded System In Just 30 Minutes
- When: 10:30 – Noon CET
- Who: Cesare Garlati, prpl Foundation and Hex Five Security; Don Barnetson, Hex Five Security
-
Trusted Execution Environments: A System Design Perspective
- When: Noon – 12:30 CET
- Who: Cesare Garlati, prpl Foundation and Hex Five Security; Boran Car, Hex Five Security
Session 6.3: Software Engineering II Design & Modeling (Feb. 27)
-
Design Cycle Acceleration for Hardware/Software Co-Design with
Renode
- When: Noon – 12:30 CET
- Who: Steve Milburn, Dover Microsystems and Michael Gielda, Antmicro
Expert Panel (Feb. 27)
-
Opportunities and Risks in Open Source Processors
- When: Noon – 13:00 CET
- Who: Cesare Garlati, prpl Foundation and Hex Five Security; Markus Levy, NXP Semiconductors; Ted Marena, Western Digital; Tim Whitfield, Arm
Read more about RISC-V activities at Embedded World here: https://riscv.org/2019/02/embedded-world-2019.
To learn more about the RISC-V Foundation, its open, free architecture
and membership information, please visit:
www.risc-v.org .
To schedule a meeting at Embedded World, please email
RISC-V@racepointglobal.com .
