MRO reduces memory latency between the memory subsystem and the SoC client -- central processing unit (CPU), graphics processing unit (GPU), codec or video processor, for example -- by providing on-demand data delivery and increasing the bandwidth between the two. Its unique programmable memory optimization capability offers in-system analysis to dynamically reconfigure an SoC's power and performance profile.
"Most memory subsystems operate at less than 80% efficiency," says Gregg Recupero, chief technology officer of Performance-IP. "The inefficiency slows the pipeline performance of the communications to and from the SoC client to the memory, even as new memory standards demand more efficiency from the memory. This needed to be improved dramatically."
Introducing Memory Request Optimizer
MRO, an advanced prefetch engine, delivers improved memory efficiency to meet the exacting requirements of today's memory standards. It is designed to analyze multiple concurrent request streams from clients to the memory then determine which requests should be optimized or prefetched. MRO analyzes multiple concurrent request streams by utilizing Performance-IP's patented Memory Tracker Technology™ to create virtual request streams, optimize memory subsystem efficiency and analyze results. This allows MRO to achieve high hit rates with low false fetch rates.
Once a request to the memory subsystem has been optimized, it is stored in the Request Optimization Buffers until needed. Buffers provide a non-blocking interface for any client interface, allowing the MRO peak response bandwidth to exceed that of the memory subsystem to reduce average memory latency.
MRO supports industry standard AXI4 and OCP on-chip interconnect specification protocol interfaces for a seamless connection to memory controllers or any other SoC client. It is delivered as a block of silicon intellectual property (IP) that can be integrated easily into an SoC's design. It can reside at any point in memory hierarchy while connecting directly to existing client and memory controllers.
In early benchmarks using mesh generation, neural network, finite difference, MP3 decode and stream benchmark, MRO produced a dramatic reduction in read latency that ranged from between 71% to 78%. The result is an increase in CPU instructions per cycle (IPC) and millions of floating point operations per second (MFLOPs). Reductions in latency improve the performance of each system component implemented in an SoC so that the design runs faster without increasing power consumption.
Performance-IP's MRO is available now and in evaluations at semiconductor companies worldwide. It is distributed as synthesizable Verilog register transfer level (RTL) source code and includes a single clock domain, fully static design, push-button synthesis and example scripts, documentation, configuration utilities and a complete verification suite. The SIP compiles on any commercially available design tool. The MRO Multi-Client Interface supports up to 16 clients and 16 memory channels.
For more information, visit: http://bit.ly/2m0BAFz
Performance-IP at IPro Technology Day in Israel
Performance-IP will participate in the IPro Group Technology Day Tuesday, March 28, at the Herods Hotel in Herzelia, Israel. Recupero will present, "Does Your Design Need More Cowbell -- Improving the Efficiency of Memory Subsystems." Details can be found at:
http://bit.ly/2n0ehAM
About Performance-IP
Performance-IP provides silicon intellectual property (SIP) to improve the memory performance of a system on chip (SoC) by reducing latency between the memory subsystem and the SoC client. Its patent-pending Memory Tracker Technology™ is incorporated into Performance-IP's flag ship products allowing system architects to recover lost system performance and reduce power consumption. Performance-IP's SIP is used worldwide by semiconductor companies. Founded in 2013, it is privately held and funded. Telephone: (781) 561-7300. Email:
info@performance-ip.com. Website:
www.performance-ip.com.
All trademarks and registered trademarks are the property of their respective owners.
For more information, contact: Nanette Collins Public Relations for Performance-IP (617) 437-1822 Email Contact