In this issue, we bring you…

• New Products & Enhancements: Meridian RDC, Ascent Lint, iDebug
• From our President and CEO, “A Paradigm Shift in Verification Methodology”
• Webinar Available online, “Ensuring Robust RTL Sign-off for Stratix FPGA and SoC Designs”
• New Lint Whitepaper available, “Setting a new Lint Benchmark”
• Press Coverage, “Real Intent: A Sustained Culture of Respect & Innovation”
• Events

New Products & Enhancements

Meridian RDC—We announced a new addition to our Meridian product family on November 15th.  Meridian RDC is the fastest and most precise reset domain crossing sign-off tool on the market. It performs comprehensive static analysis to ensure that signals crossing reset domains function reliably. Among other things, Meridian RDC identifies metastability problems arising from software and/or low power resets. Meridian RDC is the only solution that enables comprehensive reset domain crossing sign-off. It’s available now. 

Ascent Lint—We’ve made some significant enhancements to our Ascent Lint product, the industry’s fastest and most accurate tool for Lint verification of digital designs. The new 2016. A version of Ascent Lint significantly expands its coverage with more than 50 new customer-driven rules; it advances the Frontend with improved support of VHDL and System Verilog; and it provides a new database-driven debugger that offers unmatched productivity in delivering lint clean RTL.

iDebug—Database-driven debug, provided by Real Intent's new iDebug GUI and Command Line Interface, offers significantly more flexibility to users in addition to the text-based reporting. iDebug 2016.A now comes with an integrated source browser and improved schematic visualization. It offers flexible searching, sorting, and waiving. Users can waive lint violations based on post analysis status without having to re-run lint analysis.

A Paradigm Shift in Verification Methodology

Real Intent’s President and CEO, Prakash Narain, gave a presentation at the SemIsrael expo on “ A Paradigm Shift in Verification Methodology.”

Abstract:
Today’s SoCs are driving unprecedented verification complexity The combination of billions of gates, system-level functionality on a chip, complex design methodologies like asynchronous clock domains and an explosion of untimed paths on a chip, interacting dynamic power domains, aggressive reset schemes, etc. could have been the perfect storm to staunch productivity. Instead it has turned out to be the mother of all necessities that has driven significant innovation in verification and brought about a paradigm shift.

Static sign-off has proven to be a pillar in this new paradigm. This presentation discusses what has made static techniques successful and how Real Intent is delivering leading edge signoff tools.

Webinar Available Online

If you missed our webinar, “Ensuring Robust RTL Sign-off for Stratix® FPGA and SoC Designs” it was recorded and is now available online. The webinar covers the requirements for RTL sign-off including lint syntax and semantic checks, clock-domain crossing verification in the content of the FPGA flow. A solution from Real Intent is presented that reflects the practical experience by FPGA designers. To view the recorded webinar, click here. 

New Lint Whitepaper

“ Setting a new Lint Benchmark” by Lisa Piper, Technical Marketing Director. This whitepaper describes how Verilog, SystemVerilog, and VHDL design and verification can be accelerated and enhanced at all stages of development by Ascent Lint.  It also describes how Ascent Lint has set a new benchmark for linters by not only focusing on high-value rules and performance, but on the overall user experience from start to finish.

Recent Press Coverage

Peggy Aycinena interviews our President and CEO, Prakash Narain, in her blog for EDA Café; “ Real Intent:  A sustained culture of Respect & Innovation” where they discuss Dr. Narain’s views on the challenges small EDA companies face in the current business climate.

Upcoming Events

• DVCon U.S.: Mark your calendars for DVCon U.S. February 27-March 2, 2017. We’ll be exhibiting our family of advanced verification solutions during the expo in booth #605.  We invite you to come by and learn about our latest updates and offerings that accelerate the chip time-to-market using proven static verification technologies designed for accuracy, capacity and user-experience.

Recently Attended Events

• ARM Tech Symposia on November 18th in Hsinchu, Taiwan.

• SemIsrael Expo on November 15th in Airport City, Israel. In addition to participating in the Expo, our President and CEO, Prakash Narain, gave an insightful presentation, “ A Paradigm Shift in Verification Methodology.”

• Design Solution Forum on October 14th in Yokohama, Japan.

• FMCAD on September 28th in Mountain View, California. Dr. Pranav Ashar, our Chief Technology Officer, presented a tutorial to attendees. 

• CDNLive Israel on September 19th in Tel Aviv, Israel.

• DVCon India on September 15th and 16th in Bangalore, India.