SAN JOSE, Calif. — (BUSINESS WIRE) — March 14, 2013 — At DATE 2013, Calypto® Design Systems, Inc., the leader in electronic system level (ESL) hardware design and register transfer level (RTL) power optimization, will present in a technical session on an innovative approach to detecting isomorphisms in logic design and formal verification. This work is based on collaboration between Calypto and UC Berkeley that is aimed at simplifying formal analysis of circuit logic. Calypto technologies let designers create high-quality, low power ASIC and FPGA hardware products. Calypto’s three product families (PowerPro®, Catapult® and SLEC®) offer customers solutions ranging from RTL power reduction to C++/ SystemC high-level synthesis.