The ECSM statistical extensions accurately and efficiently model the impact of process and environmental variation - a potentially performance depriving problem - which can negate many of the advantages of moving to process nodes at or below 65nm. Using a statistical approach to timing analysis allows designers to unlock the true potential of smaller process technologies by reducing the pessimism that can rob chip performance in traditional design methodologies. The key to this new statistical standard is that it uses sensitivities to process and environmental device parameters to holistically model variations around nominal operating points. The statistical format accurately accounts for global, within-the-die, and random variations. The net result - fewer analysis corners, increased chip performance, and better silicon.
"Statistical analysis allows designers to understand how variation impacts their timing performance, removing the need to use overly pessimistic guard bands," said Jim McCanny, CEO of Altos Design Automation, Inc. "Using an industry standard statistical library format will enable all the key components of the design flow to adopt and benefit from statistical analysis. Indeed, Altos already supports Si2's S-ECSM format with its latest Variety 1.4 product release."
"Open standards provide an equal opportunity for EDA vendors, IDMs, fabless IC companies, and foundries to integrate into mainstream design flows and deliver innovative technology directly to end-markets," says Sumit DasGupta, sr. vice president of Si2. "We applaud the OMC for approving this important new standard for the benefit of the entire industry"
The S-ECSM specification is available for download at this link: http://www.si2.org/openeda.si2.org/projects/omcdistrib.
About the Open Modeling Coalition (OMC)
The OMC technical objectives are to define a consistent modeling and characterization environment in support of both static and dynamic library representations for improved integration and adoption of advanced library features and capabilities, such as statistical timing. The system will support delay modeling for library cells, macro-blocks and IP blocks, and provide increased accuracy to silicon for 90nm and 65nm technologies, while being extensible to future technology nodes. Member companies are: Advanced Micro Devices, Altos Design Automation, ARM, Cadence Design Systems, Extreme DA, Freescale Semiconductor, IBM, Intel, LSI, Nangate A/S, NXP Semiconductors, Renesas Technology Corp., Silicon Navigator, ST Microelectronics, Sun Microsystems, and Virage Logic. For more information on the OMC, visit: www.si2.org/?page=430.
About Si2
Si2 is an organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents over 100 companies involved in all parts of the silicon supply chain throughout the world.
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Contact:
Silicon Integration Initiative, Austin
William Bayer, 512-342-2244,
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