Verific's Verilog, VHDL and SystemVerilog parsers, analyzers and elaborators were integrated into RTLvision PRO, customizable software to help designers of intellectual property (IP)-based systems on chip (SoCs) reduce the complexity of the debug process.
Verific's HDL component software packages, which include an RTL database, are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. All products are licensed as source code and come with online support and maintenance.
Michiel Ligthart, Verific's chief operating officer, remarks: "We're delighted that our mixed-language software is an integral part of RTLvision PRO. This powerful combination is simplifying the debug process and helping designers reach RTL code closure more quickly."
"We relied on Verific to help us meet our product plan to link code with interactive graphic fragments," adds Gerhard Angst, president and chief executive office of Concept Engineering. "This partnership is effective and one that we see lasting for a long time."
Verific will demonstrate its HDL Component Software in Booth #3345 during the 43rd Design Automation Conference (DAC) starting July 24 at the Moscone Center in San Francisco. Concept Engineering will demonstrate RTLvision PRO, its RTL debugger, in Booth #720.
To schedule a demonstration during DAC, visit Verific's website located at: http://www.verific.com. Or, contact Rick Carlson, Verific's vice president of sales. He can be reached at (970) 946-1755 or via email at rick@verific.com.
About Concept Engineering
Concept Engineering, a privately held company based in Freiburg, Germany, was founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test automation and physical design tools. The company's customers are primarily original equipment EDA tool manufacturers (OEMs), in-house CAD tool developers and semiconductor companies. The company is located at Boetzinger Str. 29, D-79111 Freiburg, Germany. Telephone: +49-761-47094-0, Fax: +49-761-47094-29, http://www.concept.de.
About Verific Design Automation
Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker It develops and sells C++ source code-based SystemVerilog, Verilog, VHDL and PSL/Sugar front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: http://www.verific.com.
RTLvision PRO is a trademark of Concept Engineering. Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Contact:
Public Relations for Verific Nanette Collins, 617-437-1822 Email Contact
