The most advanced chips being introduced to the market today can cost more than $5Bn and many years to develop. Pressure to meet Return On Investment Capital (ROIC) is greater than ever.
The latest techniques in Advanced Chip Design and Manufacturing reduce the time that the package and pinout netlist have to be finalized. This shortens the system design and testing phase.
The above two conflating problem statements are addressed with the use of the Pactiv LoadSlammer.
Roger Beeston, CEO of ProGrAnalog said, "The Pactiv Solution enables 200x faster validation and testing than conventional Active or Passive testing solutions. AI plugins for Voltage Regulator Optimization (VRO) with the TeraDeep memory of the Orac controller enable Semiconductor and Systems integrators to get to market sooner."
The Pactiv LoadSlammer is a 1.5KW transient and/ or continuous power testing solution. It is architected to offer our customers the lowest Time To Market (TTM) power validation solution. The ability to test a PDN with rise/ fall times of less than 50ns enables the most rigorous of validation and characterization test benches. The 30 programmable voltage controlled current sink LoadCells are software configurable in addition to the 20 assignable differential voltage sense rails. The Orac controller is stackable to add as many Pactiv's as necessary (8 x module OAM implementation as an example).
3DSweep, Large Signal Impedance, Arbitrary Waveform Generation, AVS, PMBus telemetry, report generation, save/ share/ recall workspace and API are some of the Software features incorporated by the new Orac Controller.
Customization options to integrate the Pactiv solution into existing lab bench environments are also available.
Pactiv can be leased or purchased. Turnkey testing solutions include liquid cooling, TeraDeep Orac Memory and Waveform Controller, Pactiv head unit and all the associated Software.
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SOURCE ProGrAnalog
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