The summit aims to provide industry leaders, particularly those involved in the computer chip manufacturing sector, with essential insights into how the CHIPS Act will impact their businesses.
Keynote speaker Dr. "Chidi" Chidambaram, Ph.D, Vice President of Engineering and Qualcomm Fellow, has played a pivotal role in Qualcomm's pioneering contributions to semiconductor technologies. With over two decades of semiconductor experience, Dr. Chidambaram is recognized by the IEEE as a fellow for his contribution to strain engineering and design technology co-optimization (DTCO) and has authored over 100 referred articles and patents.
Also speaking is Ms. Deirdre Hanford, Chief Security Officer for Synopsys, is responsible for safeguarding the company while promoting secure design in EDA, IP, and Software Integrity. Dr. Hanford previously served as general manager of Synopsys' Design Group, responsible for leading the development and deployment of our physical design, implementation, and analog/mixed signal product lines. She serves on a multitude of panels and advisory boards, including the US Department of Commerce's CHIPS Industrial Advisory Committee, the Board of Directors of Cirrus Logic, Inc, the Engineering Advisory Board for UC Berkeley's College of Engineering, among others. She is co-Chair of Purdue University's Semiconductor Degrees Leadership Board (SDLB). Ms. Hanford is a board member of NDIA. Hanford was named to WomenTech's 2022 list of Women in Tech Leaders to Watch, VLSIresearch's 2017 list of All Stars of the Semiconductor Industry, and National Diversity Council's 2014 list of Top 50 Most Powerful Women in Technology.
IEEE-USA is also honored to welcome guest speaker Dr. Subramanian S. Iyer, the Director of the National Advanced Packaging Manufacturing Program (NAPMP) and a Distinguished Professor at UCLA, holding the Charles P. Reames Endowed Chair in the Electrical Engineering Department. He is also the founding Director of UCLA CHIPS (Center for Heterogeneous Integration and Performance Scaling). Previously, he served as an IBM Fellow and made significant contributions to semiconductor technology, including SiGe base HBT, Salicide, embedded DRAM, and pioneering interposer and 3D integrated products. Dr. Iyer is a distinguished fellow of IEEE, APS, iMAPS, and NAI, and he has received prestigious awards, including the IEEE Daniel Noble Medal in 2012 and the iMAPS Daniel C. Hughes Jr Memorial award in 2020.
Kathy Hayashi, IEEE Director of Region 6 (Western US Region) , expressed her excitement about the upcoming summit, stating, "The conversations started here will benefit leaders of the chip design and packaging industries for years to come. We are thrilled to host this summit in Region 6 and our greater San Diego area."
To learn more about the "Designing Chips with CHIPS: West Coast Pre-Silicon Summit" and to register for this exclusive event, please visit https://chipdesign.ieeeusa.org/.
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Event Name: Designing Chips with CHIPS: West Coast Pre-Silicon Summit
Date: November 3, 2023
Venue: Irwin M Jacobs Qualcomm Hall, Qualcomm Headquarters – Building N 5775 Morehouse Drive, San Diego, CA 92121
Event Website:
https://chipdesign.ieeeusa.org/
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