The 2020 IEEE Electronic Design Process Symposium (EDPS) is in its 27th year and continues to foster the free exchange of ideas among the top thinkers and thought leaders who focus on how chips and systems are designed in the electronics industry. This year the EDPS executive committee has decided to move this year’s symposium to a virtual event scheduled for September 30th and October 1st, 2020 due to conference participant health and safety concerns as a result of the Covid-19 pandemic.
EDPS provides a forum for this cross-section of the design community to discuss state-of-the-art improvements to electronics design processes and CAD methodologies, rather than on the functions of the individual tools themselves.
As designs get more complex, the design, test and manufacturing cycles are getting longer and more intertwined with each other. Therefore, EDPS is expanding its scope and looking beyond the classical design processes. EDPS 2020 is adding test, manufacturing, validation, and security issues as they pertain to the design of chips/systems. Each session of EDPS will offer a holistic view of design, test, validation and manufacturing issues.
This year our focus is on Smart Design and Manufacturing (CAD/Test/Manufacturing tools). We will look at new developments in systems approach to design and manufacturing and using system level techniques to reach HVM in a shorter amount of time. New techniques such as Quantum Computing, Heterogeneous Integration and Advanced Packaging, and Machine Learning for improving design processes as well as the tools will be presented. We have speakers from industry discussing integration of new techniques in their solutions. We also have speakers from academia showcasing how some of the latest research is making it into design and manufacturing processes and associated tools.
We have prominent keynotes from industry veterans on design and manufacturing trends and requirements that we will see over next five to ten years. Our keynote speakers are:
Frank Lee, TSMC VP, Heterogeneous Package-Level Integration – Trends and Challenges
Di Liang, HP Labs Sr Manager, OSA Fellow - What does it take to photonize silicon?
Andrew Miller, Ansys Granta Director of Data Products and Collaborative R&D - Materials Characterization and Modeling
Sean Lee, Facebook Architect, IEEE Fellow - Taming Carbon: toward a responsible, sustainable ecosystem for computing
Anil Rao, Intel, Vice President Data Platforms Group - “Designing Data Center Security for the Future”
David Schuster, University of Chicago Associate Professor - Designing Superconductor Circuits for Quantum Computing
Ravi Mahajan, Intel Fellow - Interconnect Scaling in Advanced Packaging Architectures
Sameer Kher, Ansys Sr Director - Leveraging Simulation-Based Digital Twins to Improve Predictive and Prescriptive Maintenance Outcomes in Manufacturing
Gerard John, Amkor Sr. Director - Using Machine Learning to Optimize Semiconductor Test
Patrick Groeneveld, Cerebras Systems, Hardware for AI
Due to the global pandemic, the event will be a virtual event that will provide a forum for EDA, design, wafer fab and packaging/test experts to address both design and manufacturing challenges. Since we cannot get together in person all media will be distributed digitally and attendees can participate in the conference for free this year. To register go to https://edps2020.eventbrite.com. For a list of speakers and abstracts visit http://www.ieee-edps.com/program1.html.
