The Gen-Z Consortium is excited to announce the public release of its Physical Layer Specification 1.1. This version provides several updates to the Gen-Z Physical Layer Specification 1.0, including enhanced support for PCIe Gen5 and support for Gen-Z 50G Fabric and Local Physical Layers. PCIe Gen5 doubles the link bandwidth from PCIe Gen4’s 16GT/s to 32GT/s per lane. Likewise, Gen-Z 50G doubles the link bandwidth of Gen-Z 25G through Four-level Pulse Amplitude Modulation (PAM4) and adds ultra-low-latency Forward Error Correction (FEC) for improved link reliability.
The Gen-Z Physical Layer Specification outlines logical, functional, electrical, and channel characteristics for a multitude of physical layers that enable communication from the Gen-Z core layers to other devices via a specific media and signaling interface. The Physical Layer Specification is formatted as a clause-based document and enables separate and subsequent development cycles for individual physical layer specification clauses required for different applications. Version 1.1 adds PCIe Gen5 support to the PCIe Physical Layer Clause and adds new clauses for the Gen-Z 50G Fabric and Gen-Z 50G Local Physical Layers.
Consortium members have released Gen-Z based IP and memory solutions, indicating the industry’s commitment to the community and in anticipation of product development. Gen-Z has eight final specifications and five draft specifications available to the public for individual and bulk download, enabling the development of products utilizing Gen-Z solutions. Download the Gen-Z Physical Layer Specification 1.1 today.
