LAWRENCEVILLE, Ga. — (BUSINESS WIRE) — September 23, 2019 — Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), announced a variety of new IP offerings on TSMC’s N5, N5P, N7, N7+, 12FFC, and 22ULP and 22ULL processes, designed to support customers’ SoC timing and clock demands.

Silicon Creations will showcase the company’s IP offerings including the “one-size-fits-all” Fractional-N PLL at TSMC 2019 Open Innovation Platform® (OIP) Ecosystem Forum in Santa Clara, Calif., September 26, 2019. The announcement is the latest from TSMC, the world’s largest foundry, and Silicon Creations, which have enjoyed over a decade-long successful partnership in taking designers to new levels of productivity and efficiency.

At TSMC 2019 OIP Ecosystem Forum, Silicon Creations will highlight a range of phase-locked loops (PLLs) shipping in products on TSMC’s most advanced process technologies. These include general-purpose Fractional-N PLLs, IoT PLLs using a 32kHz RTC reference, Low-area Core voltage PLLs and Deskew PLLs for DDR interfaces.

“Over the past six months, several customers have selected Silicon Creations’ 250Mbps to 16Gbps Multiprotocol SerDes PMA to support a wide range of protocols, including DisplayPort, V-by-One HS, JESD204B/C, Serial Rapid IO and semi-custom low-latency interfaces,” said Andrew Cole, vice president at Silicon Creations. “This initial set of protocols demonstrates the versatility of this IP, which we ported to TSMC’s 12FFC and 16FFC processes from the PMA we built for Microchip Technology’s PolarFire FPGA. We expect shortly to see customers using it for PCIe4 and 10G-KR as well. We’ve also supported several customers with an equivalent multiprotocol PMA on TSMC 40LP and TSMC 40GP processes.”

“On the PLL side, our customers have implemented at least three of our versatile Fractional-N PLLs in devices on more than a million wafers on both 28nm and 16nm. Ported to 7nm, this PLL now enables over 10 chips in mass production with tens of thousands of wafers delivered. And we’ve now seen 5nm silicon with the expected level of performance. The large number of chips using this PLL derives from its versatility,” Cole added.

TSMC OIP Ecosystem Forum attendees can learn more about Silicon Creations’ Fractional-N PLL technology at the presentation titled “Flexible clocking solutions in advanced FinFET processes from 16nm to 5nm.” The presentation, given by Cole, will start at 11:30 A.M. in the IoT & RF technical session. Attendees can also discuss their design projects and IP needs with Silicon Creations representatives at booth #519 during the TSMC 2019 OIP Ecosystem Forum.

About Silicon Creations

Silicon Creations provides world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), chip-to-chip SerDes and high-speed differential I/Os. Silicon Creations’ IP is proven from 7nm to 180nm process technologies. With commitment to customer success, its IP has an excellent record of first silicon to mass production in customer designs. Silicon Creations, founded in 2006, is self-funded and growing. The company has development centers in Atlanta, Ga., and Krakow, Poland, and worldwide sales representation. For more information, visit www.siliconcr.com.

All reference to Silicon Creations trademarks are the property of Silicon Creations, Inc. All other trademarks mentioned herein are the property of their respective owners.

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