TEWKSBURY, Mass. — (BUSINESS WIRE) — August 2, 2019 — Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of the SimAccel FPGA-based accelerator to achieve 100-1000X speed up over simulation-based verification.

“As SoCs get larger the feasibility of performing comprehensive SoC verification using purely simulation and without hardware-software co-verification is less and less practical,” said Chris Browy, VP Sales/Marketing. SimAccel provides co-emulation, hardware-software co-verification leveraging our existing VIPs and testsuites and our new synthesizable, retargetable FPGA-based Accelerator System IP (ASIP) and Accelerated VIPs (AVIP). Using design IP from Mobiveil and off the shelf FPGA prototype systems such as from Xilinx and PRO DESIGN provides the advanced hardware platforms necessary to implement multi-FPGA systems.

Highlights of the new SimAccel solution

• RTL simulation accelerator targets >100-1000X speedups over simulation
• Seamless support of simulation and accelerated VIPs
• Full line of Accelerated VIPs (AVIP) built using high quality, proven, commercial-grade design IPs including PCIe, NVMe, AMBA AXI4/AHB/APB, DDR4/LPDDR4, ONFI Flash
• Integrated HW-SW co-verification using AMBA VIP/AVIP virtual prototype (VP) adapter supporting ARM, RISC-V, and MIPs VPs including ARM Fast Models and Imperas OVPs
• Integrated unified HW-SW co-debug using SW/HW breakpointing and data structure inspection
• Multi-FPGA design partitioner targets multi-FPGA board solutions up to 16 FPGAs
• Enhanced FPGA debug visibility via Monitor AVIP supports protocol-aware debug, tracker logs, and waveforms
• Assertion-based verification (ABV) via optimized replay of accelerator traces on RTL assertions
• Utilizes commercial and customer FPGA prototype boards, Xilinx® FPGAs and tools, and other 3^rd party FPGA debug tools
• Low cost alternative by fully leveraging same investment in FPGA prototype systems, design process and tools, and engineering resources
• Comprehensive verification services to partition DUT into multiple FPGAs, integrate with ASIP/AVIP/VP IPs, implement FPGAs, and run verification on DUT

Quote from Mobiveil

“As a leading provider of high-speed serial interface IP blocks and platforms for SSD and IoT markets, we are very pleased that Avery chose Mobiveil’s PCI Express Gen5 Design IP to build this innovative simulation acceleration solution” said Ravi Thummarukudy, CEO of Mobiveil. “Avery is a long term partner and both companies have been working together on many IP/VIP partnership solutions for PCIe, NVMe, DDR, ONFI, etc.”

Quote from PRO DESIGN

“As provider of FPGA based prototyping systems, we really appreciate the partnership with Avery, which enables us to expand our proFPGA solutions into an early stage of the RTL and hardware software co-verification process. By using Avery’s SimAccel technology in combination with our proFPGA product line designers are able to catch issues in the RTL at an even earlier stage than typical FPGA based prototyping, which extends the usage of our systems a lot and which will bring significant value to our customers,” said Gunnar Scholl, CEO from PRO DESIGN Electronic GmbH.

Visit us at the Flash Memory Summit in Santa Clara during August 6-8.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, CXL, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.

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Chris Browy
(978) 851-3627