TOULOUSE, France — (BUSINESS WIRE) — March 15, 2017 — Aldec, Inc. a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGAs and ASICs, celebrates 10 years in DO-254 at Certification Together International Conference (CTIC) to be held in Toulouse, France on March 21-23, 2017.
Aldec commends its R&D, Sales/Marketing and Tech Support teams for a decade of product developments supporting customers wishing to comply with DO-254 with specialized verification tools that provide requirements management, traceability, impact analysis, HDL linting, clock domain crossings analysis, mixed-language HDL simulation, code coverage, DO-254 templates/checklists, target FPGA test system and tool qualification data packages.
“The first series of inquiries we received from customers regarding DO-254 started in early 2007, a few months after the FAA AC 20-152 was released,” said Louie De Luna, DO-254 Program Manager. “We first released DO-254/CTS™ in late 2007, and the product was immediately adopted by Thales in 2008. From that point we continued to develop more specialized products, and added three-day DO-254 classes in North America to help our customers learn DO-254 and overcome new verification challenges.”
By 2015, Aldec had worked on 50+ successful DO-254 projects for design assurance levels (DAL) A and B FPGAs using DO-254/CTS target FPGA system, and was continuing to increase tool adoption by international aviation system suppliers, including Elbit Systems.
This year, together with FAA, EASA, Airbus, Rockwell Collins, Thales and other leading avionics regulatory experts, Aldec will be presenting “Physical Testing of SoC FPGAs: A HW/SW Co-Verification Approach,” proposing new techniques of using the fully verified software according to DO-178 guidance as test vectors for testing the FPGA fabric within SoC FPGAs with embedded ARM® processor core.
“Several Aldec customers in the avionics industry are now researching new methods to verify SoC FPGAs for DAL A/B DO-254 projects,” said Krzysztof Szczur, Hardware Verification Products Manager. “One of the main problems is the lack of access to the AXI/AHB main interface at the device pin-level, making it difficult to employ requirements-based testing for the FPGA fabric. In Aldec’s technical presentation at the CTIC, we will introduce two new methods based on QEMU open-source emulator and Bus Functional Models for transaction level verification.”
Aldec’s specialized tools for design and verification of FPGAs boost productivity and help applicants achieve DO-254 compliance: Spec-TRACER, ALINT-PRO, Active-HDL and DO-254/CTS. Aldec’s tools have been implemented and deployed by several major avionics companies, accepted by certification authorities, and proven to decrease FPGA design and verification cycle from months to weeks.
About Certification Together
The Certification Together International Conference is designed to create exchanges between companies involved in airborne projects and facing certification challenges. The conference leverages the expertise of internationally recognized expert companies in the certification of critical systems.
About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, Embedded Solutions and Military/Aerospace solutions. http://www.aldec.com/
Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.
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