Grenoble, France - June 23, 2016 -  Leading-edge More-Than-Moore process variants at 55 nm for the challenges of IoT and wearable devices deserve equally state-of-the-art low power design methodologies: it involves Silicon IPs for embedding the Power Regulation Network and for the SoC Mode Control Network, together with the transfer of know-how to ensure a safe and smooth design-in.

Designers of low-power SoCs targeting 55 nm are proposed two self-contained kits, of Silicon IPs with design methodologies, at a very attractive price up until the Green Thursday, June 30. Each kit is tailored to a major SoC challenge:

1. For SoCs mostly in sleep mode: Power Regulation & Control Network kit
2. For high duty-cycle SoCs: Voltage Regulation Network kit

Such kits may be complemented with Foundation, Fabric and Feature IPs – such as standard cell libraries, memory generators, WhisperTrigger voice activity detector, uLP oscillators… – to combine the best power consumption, whatever the mode of activity of the SoC, with the smallest silicon area.
A catalog providing an overview of this consistent offering of Silicon IPs in 55 nm is immediately available on request.