Xilinx Extends SmartConnect Technology to Deliver 20 -- 30% Breakthrough in Performance for 16nm UltraScale+ Devices

Now available in the Vivado Design Suite 2016.1, SmartConnect technology solves the system interconnect bottlenecks for high performance, multi-million system logic cell designs

SAN JOSE, Calif., April 19, 2016 — (PRNewswire) — Xilinx, Inc. (NASDAQ: XLNX) today announced the 2016.1 release of the Vivado® Design Suite HLx Editions, with extensions to the SmartConnect technology, delivering unprecedented levels of performance for the UltraScale™ and UltraScale+ device portfolios. In the 2016.1 release, Vivado Design Suite includes extensions to the SmartConnect technology, solving the system interconnect bottlenecks on high density, multi-million system logic cell designs. As a result, both UltraScale and UltraScale+ device portfolios now deliver an additional 20-30% performance at high utilization.

Logo - http://photos.prnewswire.com/prnh/20020822/XLNXLOGO 

The Xilinx UltraScale+ portfolio is the only FinFET based programmable technology available in the industry. It includes Zynq®, Kintex®, and Virtex® UltraScale+ devices, and delivers 2-5X performance/watt improvement over 28nm offerings, enabling market-leading applications such as 5G wireless, software-defined networks and next-generation advanced driver-assistance systems.

The Xilinx SmartConnect technology includes a system interconnect IP, as well as new optimizations enabled by the UltraScale+ silicon innovations:

  • The AXI SmartConnect IP: Xilinx's new system connectivity generator, integrating peripherals to the user design. SmartConnect creates a custom interconnect that best matches the user's system performance requirements, thereby achieving higher system throughput at a lower area and power footprint. The AXI SmartConnect IP is available in Early Access via Vivado IP Integrator in the 2016.1 release of the Vivado Design Suite.
  • Time borrowing and useful skew optimization: These optimizations are enabled by the new UltraScale+ fine-grain clock delay insertion capability. These fully automated features mitigate large wire delays and deliver designs running at higher clock frequencies, by shifting available timing slack from the fastest paths to the critical paths of the design.
  • Pipeline analysis and retiming: These techniques allows designers to further increase performance, by adding extra pipeline stages in the design and applying automatic register retiming optimization.

Availability

The Vivado Design Suite HLx Editions and embedded software development tools 2016.1 release are now available for download. To learn more about Xilinx software development environments visit the Xilinx Software Developer Zone. To learn more about SmartConnect technology, download the backgrounder and visit http://www.xilinx.com/products/technology/smart-connect.html.

About the Xilinx UltraScale+ Portfolio                                                       

The 16nm UltraScale+ family of FPGAs, 3D ICs, and MPSoCs, combines new memory, 3D-on-3D and multi-processing SoC (MPSoC) technologies enabling an even higher level of performance and integration, and includes the SmartConnect interconnect optimization technology. Optimized at the system level, the UltraScale+ portfolio delivers value far beyond a traditional process node migration – providing 2–5X greater system level performance/watt over 28nm devices, far more systems integration and intelligence, and the highest level of security and safety.

About Xilinx

Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs, and 3D ICs. Xilinx uniquely enables applications that are both software defined and hardware optimized – powering industry advancements in Cloud Computing, SDN/NFV, Video/Vision, Industrial IoT, and 5G Wireless. For more information, visit www.xilinx.com.

#1616

#AAB851

© Copyright 2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Xilinx
Silvia E. Gianelli
(408) 626-4328
silvia.gianelli@xilinx.com

 

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/xilinx-extends-smartconnect-technology-to-deliver-20----30-breakthrough-in-performance-for-16nm-ultrascale-devices-300253247.html

SOURCE Xilinx, Inc.

Contact:
Xilinx, Inc.
Web: http://www.xilinx.com

Featured Video
Jobs
Machine Learning Engineer 3D Geometry/ Multi-Modal for Autodesk at San Francisco, California
Principal Engineer for Autodesk at San Francisco, California
Senior Principal Software Engineer for Autodesk at San Francisco, California
Manufacturing Test Engineer for Google at Prague, Czechia, Czech Republic
Senior Principal Mechanical Engineer for General Dynamics Mission Systems at Canonsburg, Pennsylvania
Equipment Engineer, Raxium for Google at Fremont, California
Upcoming Events
Digital Twins 2024 at the Gaylord National Resort & Convention Center in, MD. National Harbor MD - Dec 9 - 11, 2024
Commercial UAV Expo 2025 at RAI Amsterdam Amsterdam Netherlands - Apr 8 - 11, 2025
Commercial UAV Expo 2025 at Amsterdam Netherlands - Apr 8 - 10, 2025
BI2025 - 13th Annual Building Innovation Conference at Ritz-Carlton Tysons Corner McLean VA - May 19 - 21, 2025



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise