CEA-Leti to Share Insights into Post-7-nanometer Technologies At Workshop Prior to IEDM in Washington, D.C.
Research Includes CMOS Device Architectures, New Materials and Computing System Paradigms
GRENOBLE, France – Dec. 1, 2015 – As part of its ongoing mission to help its industrial partners implement competitive, leading-edge semiconductor capabilities, CEA-Leti will present new details about its R&D efforts in post-7-nanometer CMOS device architectures, materials and computing-system paradigms during IEDM 2015.
“Our tradition is to take a broad, production-oriented approach to technology development, to reduce risks and accelerate the transition into high-volume manufacturing, and this is our approach for the post-7nm realm,” said Olivier Faynot, manager of Leti’s Microelectronic Section. “Our interdisciplinary exploration and analysis of upstream factors, like neuromorphic computing, gives us a strategic perspective on device-level requirements, which in turn helps us evaluate options for new materials, transistor designs and integration techniques.”
Faynot will share details on the latest results on ultra-low-power atomic-scale devices at a LetiDay event on Dec. 6. He said that while electrostatics and device drivability pose important challenges, power efficiency will be the key issue in post-7nm generations, which industry roadmaps estimate will enter production in the 2019 time frame. Leti strategic marketing manager Carlo Reita noted during a LetiDays event in Grenoble earlier this year that non-recurring engineering costs for these device generations will be measured in the billions of dollars, underscoring the need for more-efficient design and implementation measures.
“We believe the solution to these power issues will be provided by a combination of new-generation CMOS logic, likely utilizing stacked nanowires, and resistive RAM memory technology, integrated using 3D approaches,” Faynot said. “This is why we have been reporting regularly on progress in these fields, as well as on new system architectures that will take best advantage of the remarkable new capabilities these devices will provide.”
Leti researcher Sylvain Barraud, who will be awarded the Paul Rappaport IEEE Prize at IEDM, demonstrated a viable integration path for stacked nanowires at the IEEE S3S Conference in October. In addition, benchmark studies demonstrate that stacked nanowires offer the best trade-off in terms of performance and parasitic capacitances, the key for energy efficiency.
Leti has about 20 scientists and engineers engaged in post-7nm development, plus an additional 10 researchers from partners, including IBM, STMicroelectronics and academic labs). Expertise ranges from solid-state physics and materials science to circuit-and-systems design and advanced manufacturing, so that potential problems are identified and addressed early on. This facilitates rapid production ramp-up and adoption of high-volume products.
About CEA-Leti (France)
As one of three advanced-research institutes within the CEA Technological Research Division, CEA Tech-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Follow us at www.leti.fr and @CEA_Leti.
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