June 09, 2015 --  Menta SAS, a provider of embedded FPGA Intellectual Property (IP), today announced its third generation of embedded FPGA (eFPGA) technology. The FPGA fabric for SoC designs provides 20 percent better power performance area than the previous generation. Menta’s eFPGA technology will be demonstrated at the Design Automation Conference in San Francisco, in booth #2716. 

“We are thrilled to showcase our enhanced eFPGA technology at DAC,” said Laurent Rougé, Founder and CEO of Menta. “The enhanced performance of our third-generation eFPGA allows customers to realize ASIC-like performance while maintaining the flexibility to accommodate any application in their SoC designs.”

Menta’s eFPGA technology features several new capabilities to help engineers achieve best-in-class performance:

• New embedded Logic Block design which includes a new Look-Up Table (LUT). This Menta’s LUT (MLUT) can be configured into a variety of LUT-based configuration, combinational functions such as full adder, comparator, equality, multiplexer and ROM.
• New full testability to allow fault coverage up to 99.8%.
• New TSMC 28nm support with several capabilities from ultra-high density to high Performance and from low power to high speed.

The enhanced eFPGA technology is based on Menta’s proven Origami tool chains, which now include synthesis to allow RTL applications in VHDL, Verilog or SystemVerilog, as well as new SDC support for application design constraints. Additionally, new timing analyses tools enhance engineer experience and facilitate designs. 

Menta licenses the eFPGA Core IP and associated software to semiconductor manufacturers.

Availability

Menta’s third generation is available now in TSMC 28 HPM. 28HPC is expected for Q3.

For more information on Menta’s eFPGA, please visit www.menta-efpga.com/technology, or contact our customer support team at Email Contact.

About Menta

Menta is a privately held company based in Montpellier, France. The company provides embedded FPGA (eFPGA) technology for System on Chip (SoC), ASIC or System in Package (SiP) designs, from EDA tools to IP generation. Menta's programmable logic architecture is based on scalable, customizable and easily programmable architecture created to provide programmability for next-generation ASIC design with the benefits of FPGA design flexibility. For more information, visit the company website at: www.menta-efpga.com 

Origami Designer, Origami Programmer and eFPGA Core IP are registered trademarks of Menta SAS. All other trademarks and tradenames are the property of their respective holders.