Belgrade, Serbia – October 22nd, 2013 ----- HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, will organize a full day seminar in Switzerland providing in-depth presentations about the challenges in today's verification of FPGA and ASIC. The seminar will include presentations from HDL Design House Verification experts, Cadence Design Systems, Germany, and uBlox Digital IC Design team.

When/Where

Tuesday, November 26th, 2013
9.00 am - 4.00 pm, lunch included
Boldern conference center
Tagungszentrum
Boldernstrasse 83
CH-8708 Männedorf
http://www.boldern.ch
To register for the seminar please visit:
http://www.hdl-dh.com/seminar.html

Participation is free of charge. Lunch and refreshments will be served.
The seminar is relevant for design & verification managers and engineers and semiconductor professionals. 

Agenda and Speakers' Topics:

9.00 - 9.30 Coffee & Registration

9.30 - 10.15 HDL Design House - Verification Expertise and PortfolioPredrag Markovic, HDL DH CEO
Bogdan Bizic, HDL DH Managing Director
HDL Design House delivers leading-edge digital and analog design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops digital and analog IP cores and offers back-end services.

10.15 - 11.15 Background, Motivation & Trends in Verification

Olivera Stojanovic, Senior Staff Verification Engineer, HDL DH
The presentation outlines the need for functional and constrained-random verification, as the best option. Benefits and key elements of Constrained Random verification are presented. The presentation also shows the latest trends in verification languages and methodology.

11.15 - 11.30 Coffee Break

11.30 - 12.30 Verification Setup and Flow
Olivera Stojanovic, Senior Staff Verification Engineer, HDL DH
The presentation addresses the topic on methodology and reuse, explaining how to create VIP and the typical VIP structure. Reusability of VIP will be described through module and top level verification. The stages of a module level verification project based on HDL DH experience will be outlined.

12.30 - 13.30 Lunch 

13.30 - 14.15 Overview of the VIP landscape from Cadence
Manfred Lehmann, Senior Account Executive
Martin Blank, Cadence Design Systems
IP Factory: Overview and IP Portfolio. The presentation provides definition of VIP and what they contain and explains the need and use of VIPs. Finally, an overview of Cadence offering in the domain of VIP is given.

14.15 - 14.45 Challenges in building the top level verification environment

Dr Jasna Mrcarica, Digital IC Design Engineer, u-blox AG
The process of building the top level verification environment is presented. Topics such as top level UVM testbench architecture and UVCs selection, HW/SW co-verification usingthe C-tests are addressed.

14.45 - 15.00 Coffee Break 

15.00 - 15.45 Hardware/Software Co-Verification
Marko Olujic, Senior Verification Engineer, HDL DH
Controlling embedded software execution by using mailbox implemented inside system memory. In this way, steps through which embedded software goes are determined by external randomization of variables used by software and by choosing externally which parts of the software will be executed. Thus, hardware behavior can be predicted and verified along with software.

15.45 - 16.00 Wrap-up & Networking 


Contact: 

Milena Jovanovic 
Marketing Manager 
HDL Design House
Phone: +381 (0) 114145557
Email: m-jovanovic@hdl-dh.com 

Frank Werner
Account Manager 
HDL Design House
Phone: +49 9531 9414401
Email: Email Contact