SANTA CLARA, Calif. — (BUSINESS WIRE) — September 30, 2013 — ATopTech, the leader in next generation physical design solutions, today announced that Aprisa™ and ApogeeTM, the company’s place and route tools, have been optimized through collaboration to help customers realize TSMC’s 16nm FinFET technology benefits of improved design performance, lower overall power consumption, and smaller area.
TSMC and ATopTech collaborated to validate the ATopTech physical implementation tools for 16FinFET technologies. The tool certification is currently in V0.5 of Design Rule Manual (DRM) and SPICE, and the collaboration will be continued to test ATopTech’s place and route tools thoroughly as TSMC 16nm FinFET technology reaches V1.0. Joint customers can now request Aprisa/Apogee Technology Files for 16FinFET directly from TSMC, helping to speed design starts and enabling smooth adoption and design success.
Aprisa and Apogee have been applied in TSMC’s 16nm FinFET Reference Flow using an ARM Cortex™-A15 quad-core processor as a validation vehicle. The key features supported by ATopTech’s Aprisa and Apogee are:
- Design enablement for 16nm FinFET DRM v0.5
- Pattern density gradient-aware floorplanning
- MiM (Metal-insulator-Metal) cap insertion
- Low-Vdd timing correlation
- High-R layer routing optimization
“ATopTech's physical implementation technology is architected specifically for advanced technology design at lower geometries to optimize performance, power and area,” said Jue-Hsien Chern, CEO of ATopTech. “Our continuing collaboration with TSMC ensures that joint customers enjoy the highest possible routability for 16nm designs.”
“We are pleased to include ATopTech’s Aprisa and Apogee in TSMC’S 16nm FinFET Reference Flow,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “The deep collaboration between ATopTech and TSMC will help enable successful 16nm FinFET projects for our joint customers.”
About ATopTech
ATopTech, Inc. is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com.
Aprisa and Apogee are trademarks and ATopTech is a registered trademark of ATopTech, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.
Contact:
Cayenne Communication LLC
Michelle Clancy, 252-940-0981
Email Contact
